The implementation of a programmable frequencydivider, which is one of the components of the phase-locked loop(PLL) frequency synthesizer for digital video broadcasting-terrestrial (DVB-T) and other modem communication systems, ispresented. By cooperating with a dual-modulus prescaler, thisdivider can realize an integer frequency division from 926 to1 387. Besides the traditional standard cell design flow, such aslogic synthesis, placement and routing, the interactions betweenfront-end and back-end are also considered to optimize the designflow under deep submicron technology. By back-annotating theback-end information to front-end design, a custom wire-loadmodel is created which is more practical compared with thedefault model. This divider has been fabricated in TSMC 0.18um CMOS technology using Artisan standard cell library. Thechip area is 675um×475um and the power consumption isabout 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency divisionwith high precision.