A limiting amplifier (LA) IC implemented in TSMC standard 0. 25μm CMOS technology is described. Active inductor loads and direct-coupled technology are employed to increase the gain ,broaden the bandwidth ,reduce the power dissipation,and keep a tolerable noise performance. Under a 3.3V supply voltage ,the LA core achieves a gain of 50-dB with a power consumption below 40mW. The measured input sensitivity of the amplifier is better than 5mVpp. It can operate at bit rates up to 7Gb/s with an rms jitter of 0.03 UI or less. The chip area is only 0.70mm × 0.70mm. According to the measurement results, this IC is expected to work at the standard bit rate levels of 2.5, 3. 125, and 5Gb/s.